chipsalliance/verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

analysisformatterhacktoberfestlanguage-server-protocollexerlinterlsp-serverparserproductivitystyle-linter

Licencia y mantenimiento

Licencia propia o modificada que GitHub no reconoce: lee el archivo LICENSE del repositorio antes de usarlo en un producto.

Último cambio de código hace 26 días.

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