chipsalliance/verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

analysisformatterhacktoberfestlanguage-server-protocollexerlinterlsp-serverparserproductivitystyle-linter

License & maintenance

Custom or modified license that GitHub does not recognise: read the LICENSE file in the repository before using it in a product.

Last code push 26 days ago.

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