pulp-platform/axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

asicaxiaxi4axi4-litefpgahardwareipnetwork-on-chiprtlsystemverilog

License & maintenance

Custom or modified license that GitHub does not recognise: read the LICENSE file in the repository before using it in a product.

Last code push 25 days ago.

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