SSealbook

syntacore/scr1

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

coreiprisc-vriscvrtlrv32erv32emcrv32irv32imcverilog

License & maintenance

Custom or modified license that GitHub does not recognise: read the LICENSE file in the repository before using it in a product.

Last code push 23 months ago.